The invention relates to the field of clock receivers, and in particular to a differential clock receiver with adjustable output timing.
A number of applications employ clock receivers that receive a clock signal and produce output signals used for the timing of other circuitry. One such application is a differential current steering digital-to-analog converter (DAC). Generally, a differential current steering DAC is a device that converts a digital value into a differential current by steering an amount of current out one or the other output of a differential output pair depending on the value of each bit in the digital word. Current steering DACs steer current out one path or the other by using differential switches in which one transistor is turned off while the other is turned on so as to steer a common current along a particular path. For such differential switches, it is important to control the on/off timing relationship between the two transistors. The on/off timing relationship is controlled by on/off signals that control the state of the transistors such that when one is turning on, the other is turning off. The on/off signals are derived from driver signals generated by a clock generator. The clock generator derives the driver signals from output signals output by a clock receiver. The clock receiver receives a clock signal and generates the output signals from the clock signal. When using such differential switches in a differential current steering DAC or other device, it is important to control the on/off timing relationship between the two transistors. In this situation, a clock receiver whose outputs have an adjustable timing relationship would be advantageous.
In one aspect, the present invention provides a differential clock receiver comprising a converter, a differential input stage, and a differential output stage. The converter converts a control signal indicative of a timing relationship into a DC offset signal. The differential input stage receives a differential clock signal and the DC offset signal. The differential input stage generates an intermediary differential signal from the differential clock. The intermediary differential signal has a DC offset resulting from the DC offset signal. The differential output stage receives the intermediary differential signal and generates at least two output signals from the intermediary differential signal. The output signals have a timing relationship determined by the DC offset of the intermediary differential signal.
In another aspect, the present invention provides a method of generating output signals with an adjustable timing relationship in a differential clock receiver. A differential clock signal is received. A control signal indicative of a timing relationship is received. The control signal is converted into a DC offset signal. An intermediary differential signal is generated from the differential clock signal and the DC offset signal. The intermediary differential signal has a DC offset resulting from the DC offset signal. At least two output signals are generated from the intermediary differential signal. The output signals have a timing relationship determined by the DC offset of the intermediary differential signal.